Getting the right optimization
Due to system real estate constraints and higher data capacity requirements, the semiconductor industry is trending towards higher density IC devices. Accordingly, device pin count and die side components tend to increase significantly, leaving minimum or insufficient contact areas on package for automated test equipment handler interface to overcome the ever increasing load force originated from test socket contacts.
A design of experiment was conducted to establish a relationship between Package KOZ, (Keep Out Zone - Device Handler Push Area), Package Size and Package Stress/Deflection during test. Ideally, KOZ is optimized to provide maximum surface area for die side components while maintaining minimum package stress/deflection during test. Over deflection can easily induce device package permanent damage (substrate de-lamination, die cracking, etc.) and unreliable electrical/thermal contacts, either will potentially cost yield loss, missing time-to-market window or premature failure in the field. We accurately measure and monitor total force and die force to ensure optimal test operation without jeopardizing the package in test.
Device material properties, provided by our customer were fed into FEA simulation software to obtain package deflection vs. handler push area relationship taking into account the plastic substrate, silicon die and under-fill compounds. Socket hardware was fabricated to facilitate actual measurement for correlation use.
Both FEA simulations and actual deflection measurements could be used to generate a formula to provide general guidelines for future test interface KOZ definitions. This formula can be adapted to meet alternative needs when package material properties and die-to-substrate ratio are changed, in accordance to package technology and market trends.